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ISD61S00 chipcorder telephony feature chip ?2008 nuvoton technology corporation america all righ ts reserved. important notice nuvoton products are not designed, intended, authorize d or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traff ic signal instruments, combustion control instruments, or for other applications intended to suppo rt or sustain life. further more, nuvoton products are not intended for applications wherein fail ure of nuvoton products could result or lead to a situation wherein personal injury, death or severe pro perty or environmental damage could occur. nuvoton customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify nuvoton for any damage s resulting from such improper use or sales. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 2 - revision 2.7 table of contents 1. general description ............................... ................................................... ............................ 3 2. features .......................................... ................................................... ......................................... 3 3. pin configuration ................................. ................................................... ................................ 5 4. pin description ................................... ................................................... .................................... 6 5. block diagram ..................................... ................................................... ................................... 9 6. application reference schematics .................. ................................................... .......... 10 6.1 pcb layout guidelines ............................. ................................................... ................. 10 7. package specification ............................. ................................................... ......................... 14 7.1 lqfp48l (7x7x1.4mm footprint 2.0mm) ............... ................................................... ..... 14 8. electrical characteristics ........................ ................................................... ................... 15 8.1 absolute maximum ratings .......................... ................................................... .............. 15 8.2 operating conditions .............................. ................................................... .................... 15 8.3 dc parameters ..................................... ................................................... ...................... 16 8.4 analog transmission characteristics ............... ................................................... .......... 17 8.5 analog distortion and noise parameters ............ ................................................... ....... 17 8.5.1 8khz sampling ..................................... ................................................... ........................ 17 8.5.2 16khz sampling .................................... ................................................... ....................... 18 8.6 spi timing ........................................ ................................................... .......................... 18 8.7 recommended clock/crystal specification ........... ................................................... .... 19 8.8 dual tone alert signal (cas) ...................... ................................................... ............... 20 8.9 fsk detection C 1200baud bell 202, itu v.23, 300 ba ud bell 103, itu v.21 ............. 21 8.10 fsk transmitter C bell 202, itu-v.23, bell 103, itu -v.21 ........................................... 2 3 8.11 dtmf detection .................................... ................................................... ..................... 24 9. ordering information............................... ................................................... ........................ 25 10. revision history .................................. ................................................... ................................ 26 www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 3 - revision 2.7 1. general description the ISD61S00 is a feature chip for the security and telephony industry. the device incorporates audio storage with a powerful macro scripting ability to facilitate audio prompting in a multi-language environment and simple address-free recording and p layback. it utilizes external serial flash memory f or audio data storage. in addition, the device include s circuitry to perform telephony based data communications including dtmf detection and generat ion, fsk modem functions from 75-1200 baud, cas and cpt (call progress tone) detection and ring detection. the audio path of the device is designed to interface to both the air side and line side of a pstn system. the air side includes a fle xible microphone interface incorporating a bias generator and gain control and a differential analog output for driving a speaker or power amplifier. the line side incorporates a line driver to drive pstn loads and two variable gain differential inputs. the audio path i ncludes full and half-duplex acoustic and line echo cancellation to implement full and half-duplex spea kerphone functions. the digital audio interface can be configured to i 2 s or pcm mode for digital serial audio communicatio n. control, monitoring and device programming is perfomed via a spi interface. the de vice package is lqfp-48l. 2. features external memory: o the ISD61S00 supports the following flash: manufacturer winbond numonyx mxic family 25x 25q 25p 25px 25pe 25l / 25v jedec id ef 30 1x ef 40 1x 20 20 1x 20 71 1x 20 80 1x c2 20 1x o the addressing ability of ISD61S00 is up to 128mbi t, which is 64-minute record/playback time based on 8khz/4bit adpcm. fast pre-recording: recording is limited by the wr ite rate of the attached external flash. operating voltage: 2.7-3.6v. sampling frequency: recording and playback samplin g frequencies of 4, 5.3, 6.4, 8, 10.6, 12.8 and 16 khz. compression algorithm: o for record and playback: o adpcm compression at 2, 3, 4 or 5 bits per sample. o -law companding at 6, 7 or 8 bits per sample. o differential -law encoding at 6, 7 or 8 bits per sample. o pcm encoding at 8, 10 or 12 bits per sample. for pre-recorded audio playback (voice prompts) ad ditionally: o enhanced adpcm compression at 2, 3, 4 or 5 bits pe r sample. o multi-bit rate optimized compression. this allows best possible compression given a metric of snr and background noise levels. message management: o simple address free real-time recording. o flexible voice prompt message management and voice macro scripting for pre-recorded messages. external serial flash memory interface: support up to 128mbit for audio and digital data storage, equivalent to 64 minutes based on 8khz 4bit adpcm. digital access to flash memory: memory can be rese rved on a 4kbyte sector basis for use as www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 4 - revision 2.7 conventional digital memory by host. telephony/modem/data features at 8khz codec sampli ng rate: o dtmf encoder with 20 digit dial string buffer. o dtmf detector. o fsk generation at 75/110/150/300/1200 baud for bel l 103, bell 202, v.21 or v.23 modem standards. transmit fifo to reduce host interaction . o fsk detector at 75/110/150/300/1200 baud for bell 103, bell 202, v.21 or v.23 modem standards with receive fifo. o ring detector. o call progress tone (cpt) detector for detecting di al tones, busy tones etc. o cas detector for caller id type i, type ii impleme ntation. o arbitrary dual tone generator. o arbitrary tone detector. acoustic echo cancellation (aec), line echo cancel lation (lec) and automatic gain control (agc) for on-chip speakerphone support. up to 17 gpio pins accessible through the spi inte rface. audio input: o ti1 and ti2: differential analog inputs for pstn i nterface (on-hook and off-hook). o mic+/-: analog interface to microphone. audio output: o po: differential analog output for pstn interface. o spk: differential output buffer for speaker driver . i/o: o spi interface: miso, mosi, sclk, ss for commands a nd digital audio data. o int and r/b signal for signaling and flow control. package: green lqfp-48l temperature: -40 c to 85 c www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 5 - revision 2.7 3. pin configuration gpio<10> gpio<12> gpio<11> gpio<9>/sdi1 gpio<8>/sdo1 gpio<7>/sdi gpio<6>/sck gpio<5>/ws gpio<4>/sdo di csb auxout ti2n ti1p ti2p gpio<15>/rdet gpio<16>/rdet miso sclk ssb mosi rdy_bsyb nc ti1n figure 3-1 ISD61S00 48-lead lqfp pin configuration. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 6 - revision 2.7 4. pin description pin number pin name i/o function drive 1 reset i a 10ms high pulse (0v to vcc to 0v ) will reset the chip n/a 2 intb o active low interrupt request pin. this pin has an open drain output. 4/8ma 3 gpio<14>/rdet i/o* general purpose io pin or the ring detect input (rdet). 4/8ma 4 vssd g digital ground. n/a 5 xtalout o crystal interface output pin. n/a 6 xtalin i crystal interface input pin. it can also be used to provide an external clock to the device. n/a 7 vddl o this pin has a nominal 1.8v output to supply the internal logic. a 2.2nf capacitor should be connected to this pin. n/a 8 vccd p digital power supply pin n/a 9 vssd g digital ground. n/a 10 gpio<13>/rdet i/o* general purpose io pin. 4/8m a 11 do/gpio<0> i/o flash interface data out. alternatively general purpose io pin. 4/8ma 12 clk/gpio<1> i/o flash interface clock. alternatively general purpose io pin. 4/8ma 13 csb o flash interface chip select bar. 4/8ma 14 di i flash interface data in. 4/8ma 15 gpio<4>sdo i/o* general purpose io pin. serial data out for the i2s interface. 8/16ma 16 gpio<5>/ws i/o* general purpos e io pin. word select (ws) output for the i2s interface 8/16ma 17 gpio<6>/sck i/o* general purpose io pin. serial clock output for the i2s interface 8/16ma 18 gpio<7>/sdi i/o* general purpose io pin. serial data input (sdi) input pin for the i2s interface. 8/16ma 19 gpio<8>/sdo1 i/o* general purpose io pin. secondary serial data out for the i2s interface. 4/8ma 20 gpio<9>sdi1 i/o* general purpose io pin. secondary serial data input (sdi) input pin for the i2s interface. 4/8ma www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 7 - revision 2.7 21 gpio<10> i/o* general purpose io pin. 4/8ma 22 gpio<11> i/o* general purpose io pin or the ring detect input (rdet). 4/8ma 23 gpio<12> i/o* general purpose io pin. 4/8ma 24 auxout o auxiliary output from pstn or speaker d ac. n/a 25 vssa g analog ground pin n/a 26 spkn o negative speaker driver output n/a 27 po- o negative line driver output n/a 28 vcca p analog power pin n/a 29 po+ o positive line driver output n/a 30 spkp o positive speaker driver output n/a 31 vssa g analog ground pin n/a 32 mcgnd i analog ground pin for mic. this pin should be connected to a quiet vssa and used as the return for microphones connected to mcp. n/a 33 mco i/o mic feedback signal n/a 34 mcp i positive mic signal input. n/a 35 vbg i/o voltage reference, a 100nf capacitor should be connected to this pin. n/a 36 vmid i/o voltage reference, a 4.7uf capacitor should be connected to this pin. n/a 37 ti1p i pstn line #1 positive input n/a 38 ti1n i pstn line #1 negative input n/a 39 ti2p i pstn line #2 positive input n/a 40 ti2n i pstn line #2 negative input n/a 41 gpio<15>/rdet i/o* general purpose io pin. can be configured as ring detect (rdet) input. 4/8ma 42 gpio<16>/rdet i/o* general purpose io pin. can be configured as ring detect (rdet) input. 4/8ma 43 miso o spi slave serial data output from the ISD61S00 to the host. this pin is tri-stated when ssb=1. 4/8ma 44 sclk i spi serial clock input to the ISD61S00 from the host. n/a 45 ssb i slave select input to the ISD61S00 from th e host n/a 46 mosi i spi slave serial data input to the ISD61S00 from the host. 4/8ma www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 8 - revision 2.7 47 rdy/bsyb o this pin is at vccd when the chip is ready to accept a new command/data and is at vssd when device is busy. 4/8ma 48 nc n/a no connect n/a * default state for digital i/o pins is input with internal pull-up [38kohms to 83kohms] to vccd suppl y www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 9 - revision 2.7 5. block diagram adc dac aec adc dac lec compression decompression flashmemorycontroller spiinterface memorymanagement andcommand interpreter sclk ssb miso mosi intb rdy/bsyb mux and mix mcp mco po po1p ti1p dtmfdetection dtmfgeneration fskgeneration fskdetection i2sinterface sck ws sdo sdi ti1 ti2 ti1n ti2p ti2n po1n spk spkp spkn mic mcgnd a micbias auxout aux stage1 stage2 figure 5-1 ISD61S00 block diagram www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 10 - revision 2.7 6. application reference schematics the bottom part of figure 6-1 shows a reference des ign for a pstn interface to the ISD61S00. two analog signal paths are provided for monitoring aud io signals on tip and ring. the type 1 cid is for monitoring tip and ring in an on-hook state to rece ive cid information. the type ii cid and speech interface is through a balanced configuration along with the output driver for use when the signal pat h is off-hook. also included are optional circuits for l ine detection, ring detection and pulse dialing. the figure 6-2 illustrates a reference design for c onnecting the ISD61S00 to an integrated silicon daa . 6.1 pcb layout guidelines to gain maximum performance from the ISD61S00 it is important to provide clean analog supplies to the device. separate vcca and vssa returns to the board low impedance point are essential for noise isolation. good quality low esr decoupliling capaci tors on the supplies along with filter capacitors o n vbg and vmid are also important for optimal performance . care in shielding mic connections from noise sources is imperative, these connections should be as short as possible and shielded with vssa. the speaker and po connections carry high currents and should be made as wide as possible. the ti inputs are differential and should be run as a pair and sh ielded with vsaa. the flash spi bus is a high speed serial bus and connections should be routed to the flash device in equal and short traces. u1 isd61sxx 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 29 30 31 32 33 34 35 36 41 42 43 44 45 46 47 48 9 10 11 12 21 22 23 24 28 27 26 25 40 39 38 37 reset intb gpio14/rdet vssd xtalout xtalin vddl vccd csb di gpio4/sdo gpio5/ws gpio6/sck gpio7/sdi gpio8/sdo1 gpio9/sdi1 po+ sp+ vssa mcgnd mco mcp vbg vmid gpio15/rdet/ti3p gpio16/rdet/ti3n miso sclk ssb mosi rdy/bsyb nc vssd gpio13/rdet do clk gpio10 gpio11 gpio12 auxout vcca po- sp- vssa ti2n ti2p ti1n ti1p c16 1nf ti1n dvdd r7 10k c9 .1uf spiflash interface po+ pulse_dial po- loop_det i2s interface sw1 r6 10k c17 .1uf c18 4.7uf mk1 microphone 1 2 avdd c10 .01uf ti2n r9 1m to microcontroller ti1p ls1 speaker hook_ctrl r8 270r c20 12pf c19 12pf ti2p y1 12.288mhz ring_det c8 .01uf hook_det c7 .1uf www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 11 - revision 2.7 r62 10m gpio11 daa_loop_det gpio13/rdet c37 .1uf q5 mmbt3904 3 2 1 c50 .47_650v gpio10 r50 4.7k gndb r45 27k r63 10m r59 5.6m gnde daa_po+ c52 470pf_500v d9 1n4001 r58 4.7k d10 1n4001 discretedaa iso3 pc817 1 2 4 3 c43 nopop gpio15/rdet/ti3p ti2p r43 10k_1206 q2 mmbta42 3 1 2 d5 2.4v tip r104 6.8k daa_ti2p gpio14/rdet daa_hook_ctrl d13 led tp44 1 daa_ti1p daa_hook_det c53 470pf_500v avdd tp49 d11 diode gnde ti2n d4 2.4v r64 2.2k gndb daa_hook_ctrl iso2 cpc1230 1 2 4 3 daa_ti2p r65 0 avdd gpio13/rdet daa_ring_det r53 220 po- daa_loop_det daa_ti2n daa_hook_det gnde gpio10 ring gpio14/rdet r60 10m r39 300 gpio15/rdet/ti3p c38 12uf_100v j12 rj11 1 2 3 4 5 6 avdd daa_ti1n d8 15v ti1n gndb gnde d3 2.4v c48 .0047uf gpio12 tp50 gnde daa_po- daa_pulse_dial tp43 1 avdd daa_ring_det iso4 pc817 1 2 4 3 ti2p r54 4.7k po+ r55 220 ti2n r47 10k_1206 + - ~~ d6 bridge 4 1 3 2 r42 300 ti1p c51 470pf_500v c44 nopop iso1 pc817 1 2 4 3 c54 1uf _100v r52 68/2w r48 4.7k ti1p daa_ti1p r40 100k note 1: eval board currently setup for resistive t ermination. this is an as is schematic which does not necessary match country s pecific requirements. fb2 mmz2012r601a r56 220 d12 1n4001 daa_ti1n + c41 10uf daa_ti2n gpio11 r41 100k avdd daa_po+ t1 ats-488 1 6 3 4 c40 .1uf r46 10k_1206 c49 .0047uf gpio12 c45 47nf gndb c39 12uf_100v gndb avdd r66 3.9m po- q4 mmbt3904 3 2 1 r57 4.7k r51 47 po+ daa_po- c55 1uf_50v(x5r) daa_pulse_dial c42 0.1uf r49 1k c47 2.2uf impedance matching (add silk screen) + - ~~ d14 bridge 4 1 3 2 q3 pzta42 1 2 3 4 avdd ti1n iso5 pc817 1 2 4 3 gnde r38 0 sw11 dil switch 12 smt ckn6109-nd / sda12h1sbd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 u4 max917 5 4 1 2 3 vcc in- out vee in+ r44 10k_1206 q6 bc817-40 3 2 1 d7 p3100sc 1 2 fb1 mmz2012r601a r61 47k c46 .33uf figure 6-1 application reference schematic with dis crete daa www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 12 - revision 2.7 u1 isd61sxx 1 2 3 4 5 6 7 8 13 14 15 16 17 18 19 20 29 30 31 32 33 34 35 36 41 42 43 44 45 46 47 48 9 10 11 12 21 22 23 24 28 27 26 25 40 39 38 37 reset intb gpio14/rdet vssd xtalout xtalin vddl vccd csb di gpio4/sdo gpio5/ws gpio6/sck gpio7/sdi gpio8/sdo1 gpio9/sdi1 po+ sp+ vssa mcgnd mco mcp vbg vmid gpio15/rdet/ti3p gpio16/rdet/ti3n miso sclk ssb mosi rdy/bsyb nc vssd gpio13/rdet do clk gpio10 gpio11 gpio12 auxout vcca po- sp- vssa ti2n ti2p ti1n ti1p c16 1nf ti1n dvdd r7 10k c9 .1uf spiflash interface po+ pulse_dial po- loop_det i2s interface sw1 r6 10k c17 .1uf c18 4.7uf mk1 microphone 1 2 avdd c10 .01uf ti2n r9 1m to microcontroller ti1p ls1 speaker hook_ctrl r8 270r c20 12pf c19 12pf ti2p y 1 12.288mhz ring_det c8 .01uf hook_det c7 .1uf gpio12 clare_ringfull r17 301r c5 .01uf ti1p ti1n clare_ring ti2n in- tp48 r93 10m r5 6.49m r24 1.8m,1/10w,1% clare_ti1p r6 261k gndc c2 0.1uf r95 806k clare_po- gpio11 in+ clare_hook_det sw1 dil switch 12 smt ckn6109-nd / sda12h1sbd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 gndc gpio15/rdet/ti3p + c1 10uf clare_mode r102 118k gpio12 j2 rj11 1 2 3 4 5 6 c16 220pf,2000v,5% clare_loop_det r9 1.69m r19 0 gpio10 clare_ti1n clare_ti1n r101 26.7k r99 17.8k clare_ringhalf r94 10m gpio14/rdet clare_po+ c11 .1uf,16v r13 200k fb3 mmz2012r601a po- r8 499k c8 .1uf,16v gndc gpio14/rdet r21 1.8m,1/10w,1% r23 1.8m,1/10w,1% c6 .1uf,16v avdd note 1: eval board currently setup for resistive t ermination for resistive termination: r6 = 261k; r8 = 499k; r15 = 221k; r16 = 3.32k; r17 = 301r; r19 = 0r; c15 = not populated; c13 = 15pf for reactive termination: r6 = 110k; r8 = 221k; r15 = 200k; r16 = 10k; r17 = 59r; r19 = 169r; c15 = 0.68uf ; c13 = not populated ; note 2: this is an as is schematic, refer to clare (tm) datasheet and application notes for any changes po- r96 10m r100 80.6k c78 0.1uf avdd avdd gpio15/rdet/ti3p r18 68.1r c17 220pf,2000v,5% ti2p u1 cpc5622 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 vdd txsm tx- tx+ tx modeb gnd ohb ringb ring2b rx- rx+ snp+ snp- rxf rx vddl rxs rpb br- zdc dcs2 dcs1 ntf gat nts br- txsl znt ztx txf refl + c3 10uf, 16v gpio11 l1 600r, 200ma; murata blm11a601s r2 80.6k c9 .1uf,16v r1 10r 1/16w 5% in- c10 .1uf,16v r15 221k clare_loop_det j46 jumper 1 2 3 gndc ti1p r3 60.4k gpio13/rdet r4 1m gndc clare daa 1.0 isd-es6100_usb rev-b c 1 4 thursday , july 29, 2010 title size document number rev date: sheet of po+ q1 cpc5602c gndc c12 100pf,16v clare_tip gndc c13 15p c14 .027uf,16v impedance matching (add silk screen) gndc d2 p3100ea/to_1 1 2 cp_ring fb4 mmz2012r601a avdd ti1n r20 1.8m,1/10w,1% cp_tip r103 6.8k + c4 1uf, 16v clare_hook_ctrl gpio10 gpio13/rdet ti2p clare_hook_ctrl r22 1.5m r97 10m clare_ringfull clare_po- tp45 1 + - ~~ d1 diode bridge_1 4 1 3 2 r98 26.7k clare_po+ gndc u11 cpc5712 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vcc det2 det1 polarity out+ out- in+ in- vref vl1 vh1 vl2 vh2 not_used not_used gnd claredaa gndc gndc r12 2r,5% clare_ti1p avdd c7 .01uf,500v ti2n tp47 c15 no pop r10 8.2r,1/8w,1% in+ clare_hook_det clare_ringhalf po+ r11 6.49m r7 47r,5% r14 130k r16 3.32k http://www.clare.com/products/litelink.htm www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 13 - revision 2.7 figure 6-2 application reference schematic with int egrated clare daa www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 14 - revision 2.7 7. package specification 7.1 lqfp48l (7x7x1.4mm footprint 2.0mm) www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 15 - revision 2.7 8. electrical characteristics 8.1 absolute maximum ratings condition value junction temperature 150 0 c storage temperature range -65 0 c to +150 0 c lead temperature (soldering C 10 seconds) 300 0 c lqfp-48l thermal resistance, typical 76 c/w (ase) 60c/w (greatek) tbd voltage applied to any pin (v ss - 0.3v) to (v dd + 0.3v) input current applied to any digital input pin +/- 10 ma esd (human body model) 2000 v v dd - v ss -0.5v to +3.63v v ddl - v ss -0.5v to + 1.98v device power dissipation 0.18 watt (tbc) stresses above those listed may cause permanent da mage to the device. exposure to the absolute maximum ratings may affect device reliabil ity. functional operation is not implied at these conditions. 8.2 operating conditions operating conditions (commercial packaged parts) conditions values operating temperature range (case temperature) 0c to +70c supply voltage (v dd ) [1] +2.7v to +3.6v ground voltage (v ss ) [2] 0v input voltage (v dd ) [1] 0v to 3.6v voltage applied to any pins. (v ss C0.3v) to (v dd +0.3v) operating conditions (industrial packaged parts) conditions values operating temperature range (case temperature) -40 c to +85c supply voltage (v dd ) [1] +2.7v to +3.6v ground voltage (v ss ) [2] 0v input voltage (v dd ) [1] 0v to 3.6v www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 16 - revision 2.7 voltage applied to any pins (v ss C0.3v) to (v dd +0.3v) notes: [1] v dd = v cca = v ccd [2] v ss = v ssa = v ssd 8.3 dc parameters parameter symbol min typ [1] max units conditions supply voltage v dd 2.7 3.6 v input low voltage v il v ss -0.3 0.3xv dd v input high voltage v ih 0.7xv dd v dd v schmitt trig. low to high threshold point vt+ 1.49 1.54 1.58 v schmitt trig. high to low threshold point vt- 1.24 1.29 1.34 v pull-up resistor r pu 38 54 83 k pull-down resistor r pd 25 49 110 k output low voltage v ol 0.4 v i ol = 3a intb output low voltage v ol1 0.4 v output high voltage v oh 2.4 v i oh = -10a internal logic supply v ddl 1.65 1.8 1.95 v analog outputs dc level v dc av dd / 2 v @ +27c half supply reference v mib 1.65 v av dd = 3.3v @ +27c bandgap reference v bg 1.218 v av dd = 3.3v @ +27c operating current (outputs loaded: 8 ohm 120 ohm) i dd_max 150 ma av dd = 3.6v, loaded, sampling freq = 8 khz, all blocks enabled, full scale. operating current (outputs not loaded: 8 ohm 120 ohm) i dd_max 45 ma av dd = 3.6v, no load, sampling freq = 8 khz, all blocks enabled, full scale. standby current i sb 11 20 a av dd = 3.6v @ +27c input leakage current i il 10 a force av dd notes: [1] conditions v dd =3.3v, t a =25c unless otherwise stated www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 17 - revision 2.7 8.4 analog transmission characteristics avdd=3.3v ; v ss =0v; t a =+27 c; all adc tests using auxiliary input mode @ 0db g ain parameter sym condition typ transmit (adc) receive (dac) unit min max min max dc level v dc dc level on the outputs spp C spn; pop - pon av dd /2 -- -- 1.35 1.8 v full scale level t xmax adc (single ended) dac (differential) 1.35 2.7 1.05 2.1 --- --- 1.05 2.1 --- --- v pk v pk absolute gain g abs -3dbfs @ 1020 hz, avdd =3.3v; t a =+25 c; 0 -0.40 +0.40 -0.40 +0.40 db absolute gain variation with supply voltage g abss avdd=3.13v C 3.47v; - 3dbfs @ 1020 hz; t a =+25 c 0 -0.50 +0.50 -0.50 +0.50 db 8.5 analog distortion and noise parameters all adc tests using auxiliary input mo de @ 0db gain 8.5.1 8khz sampling avdd=3.3v; v ss =0v; t a =+27 c; 8khz sampling, high osr selected (0x040[5]=1b1), dither turned off (0x151[0]=1b0, 0x141[0]=1b0) parameter sym condition transmit (a/d) receive (d/a) unit min typ max min typ max signal to noise ratio snr idle channel a-weighted 80 90 -- 80 90 -- db total harmonic distortion thd -3dbfs @ 1020 hz, 8ohm speaker load a-weighted -- 0.01 0.018 -- 0.16 0.5 % frequency response f low -3db low pass cut-off 3.36 3.36 khz power supply rejection psrr a v cca ; 35mvrms dc to 3.4 khz, differential inputs and outputs, a-weighted, -- 50 -- -- 50 -- db www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 18 - revision 2.7 8.5.2 16khz sampling avdd=3.3v; v ss =0v; t a =+27 c; 8khz sampling, high osr selected (0x040[5]=1b1), dither turned off (0x151[0]=1b0, 0x141[0]=1b0) parameter sym condition transmit (a/d) receive (d/a) unit min typ max min typ max signal to noise ratio snr idle channel a-weighted 80 90 -- 80 90 -- db total harmonic distortion thd -3dbfs @ 1020 hz, 8ohm speaker load a-weighted -- 0.01 0.018 -- 0.16 0.5 % frequency response f low -3db low pass cut-off 6.73 6.73 khz power supply rejection psrr a v cca ; 35mvrms dc to 6.8 khz, differential inputs an outputs, a-weighted -- 50 -- -- 50 -- db 8.6 spi timing t rise t fall ssb sclk mosi miso t sck t sckh t sckl t ssbs t ssbh t mos t moh t mid t ssbhi t zmid rbb t crbd t rbcd t mizd figure 8-1 spi timing www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 19 - revision 2.7 symbol description min typ max unit t sck sclk cycle time 100 --- --- ns t sckh sclk high pulse width 45 --- --- ns t sckl sclk low pulse width 45 --- --- ns t rise rise time for all digital signals --- --- 10 ns t fall fall time for all digital signals --- --- 10 ns t ssbs ssb falling edge to 1 st sclk falling edge setup time 60 --- --- ns t ssbh last sclk rising edge to ssb rising edge hold time 30 --- --- ns t ssbhi ssb high time between ssb lows 50 --- --- ns t mos mosi to sclk rising edge setup time 45 --- --- ns t moh sclk rising edge to mosi hold time 15 --- --- ns t zmid delay time from ssb falling edge to miso active - - -- 12 ns t mizd delay time from ssb rising edge to miso tri-state -- -- 12 ns t mid delay time from sclk falling edge to miso --- --- 40 ns t crbd delay time from sclk rising edge to rbb falling edge -- -- 12 ns t rbcd delay time from rbb rising edge to sclk falling edge 0 -- -- ns 8.7 recommended clock/crystal specification the following crystal or external master clock spec ifications are recommended for a correct operation. parameter limit values unit condition min. typ. max. frequency 7.56 12.288 32.768 mhz fundamental mode load capacitance 18 pf dynamic capacitance cc 22.12 ff resonance resistance rc 40 w electrostatic capacitance 5.1 pf www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 20 - revision 2.7 8.8 dual tone alert signal (cas) ac electrical characteristics C dual tone aler t signal detection description sym. min typ max units no test low tone frequency f l 2130 hz high tone frequency f h 2750 hz frequency deviation acceptation 1.0 3.0 % 1 frequency deviation rejection 3.5 % 2 accept signal level per tone -40 -37.78 -2 0.22 dbv dbm s/n=20 3, 5, 7 reject signal level per tone -46 -43.78 dbv dbm s/n=20 4, 5, 7 positive and negative twist accept -10 10 db s/n=20 6, 7 signal to noise ratio 20 db 5, 6, 7 notes: 1. the range within which tones are accepted. 2. the range outside of which tones are rejec ted. 3. this applies bt specification that has cov ered the requirements of bell core. 4. this applies mitel mt8843 specification. w inbond w91030a: -44 dbm, newave nw6006: -47 dbv and cli cmx602a: -46 dbv. 5. these characteristics are for avdd=3.3v an d 25 c. 6. both tones have the same amplitude and at the nominal frequencies. twist f amplitude f amplitude h l = ?? ? ?? ? 20 log 7. band limited random noise 300~3400 hz. mea surement valid only when the tone is present. ac timing characteristics C dual tone alert s ignal detection symb ol description min typ max units notes t casdp alert signal present detect time 0.5 1.88 10 ms 1 t casda alert signal absent detect time 0.5 1.46 10 ms 2 notes: 1. t casdp typical time corresponding to 4 cycles of low tone 2. t casda typical time corresponding to 4 cycles of high ton e www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 21 - revision 2.7 8.9 fsk detection C 1200baud bell 202, itu v.23, 30 0 baud bell 103, itu v.21 ac electrical characteristics C fsk detection description sym. min typ max units notes input frequency detection bell 202 1 (mark) mark f 1188 1200 1212 hz bell 202 0 (space) f space 2178 2200 2222 itu-t v.23 1 (mark) 1280.5 1300 1319.5 itu-t v.23 0 (space) 2068.5 2100 2131.5 transmission rate 1200 baud 1% 150 baud 1% 75 baud 1% input detection level per tone -40 -37.78 -6.2 -4.0 dbv dbm s/n=20 1,3 reject signal level per tone -48 -45.78 dbv dbm s/n=20 1,3 positive and negative twist accept -10 10 db s/n=20 2,3 signal to noise ratio 20 db s/n=20 3 description sym. min typ max units notes input frequency detection bell 103 1 (mark), high band mark f 2213 2225 2237 hz bell 103 0 (space), high band f space 2013 2025 2037 hz bell 103 1 (mark), low band mark f 1258 1270 1282 hz bell 103 0 (space), low band f space 1058 1070 1082 hz itu-t v.21 1 (mark), high band mark f 1638 1650 1662 hz itu-t v.21 0 (space), high band f space 1838 1850 1862 hz itu-t v.21 1 (mark), low band mark f 968 980 992 hz itu-t v.21 0 (space), low band f space 1168 1180 1192 hz transmission rate 300 baud 1% 110 baud 1% input detection level per tone -40 -37.78 -6.2 -4.0 dbv dbm s/n=20 1,3 reject signal level per tone -48 -45.78 dbv dbm s/n=20 1,3 positive and negative twist accept -10 10 db s/n= 20 www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 22 - revision 2.7 2,3 signal to noise ratio 20 db s/n=20 3 notes: 1. these characteristics are for avdd=+3.3v and 25 c. 2. both mark and space have the same amplitude and at the nominal frequencies. twist amplitude of f amplitude of f mark space = ?? ? ?? ? 20 log 3. band limited random noise (200~3400 hz). measuremen t is valid only when the fsk signal is present. not e that the bt band is 300~3400 hz, while the bell core band is 0~4k hz. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 23 - revision 2.7 8.10 fsk transmitter C bell 202, itu-v.23, bell 103 , itu-v.21 modulation rates and characteristic frequencies for the forward data-transmission channel description sym min typ max units notes twist -0.5 0 0.5 % baud rate 1200 baud 1% bell 202 1 (mark) mark f 1197 1200 1203 hz 3 0 (space) space f 2197 2200 2203 hz 3 v.23 1 (mark) mark f 1297 1300 1303 hz 3 0 (space) space f 2097 2100 2103 hz 3 description sym min typ max units notes twist -0.5 0 0.5 % baud rate 300 baud 1% 110 baud 1% bell 103 1 (mark), high band mark f 2222 2225 2228 hz 3 0 (space), high band space f 2022 2025 2028 hz 3 1 (mark), high band mark f 1267 1270 1273 hz 3 0 (space), high band space f 1067 1070 1073 hz 3 v.21 1 (mark), high band mark f 1647 1650 1653 hz 3 0 (space), high band space f 1847 1850 1853 hz 3 1 (mark), low band mark f 977 980 983 hz 3 0 (space), low band space f 1177 1180 1183 hz 3 * tx signal % baud or bit rate accuracy is the same a s xtal/clock % frequency accuracy . www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 24 - revision 2.7 8.11 dtmf detection ac electrical characteristics C dtmf detection description sym min typ max units notes frequency deviation acceptation 2.0 % frequency deviation rejection 3.5 % accept signal level per tone -36 -6 dbm reject signal per tone -46 dbm positive and negative twist accept 10 db s/n=20 signal to noise ratio 20 db www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 25 - revision 2.7 9. ordering information i61s00 fyi lead-free package type f: 48l-lqfp y: green (rohs compliant) temperature i: industrial -40 c to 85 c www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 26 - revision 2.7 10. revision history versi on date page description 2.5 may 5, 2010 update pin-out diagram. update block diagram. 2.6 sep 28, 2010 add table of supported serial flash memory. 2.7 mar 10, 2011 update spi timing spec. important notice nuvoton products are not designed, intended, author ized or warranted for use as components in systems or equipment intended for surgical implanta tion, atomic energy control instruments, airplane or spaceship instruments, transportation i nstruments, traffic signal instruments, combustion control instruments, or for other applic ations intended to support or sustain life. furthermore, nuvoton products are not intended for applications wherein failure of nuvoton products could result or lead to a situation wherei n personal injury, death or severe property or environmental damage could occur. nuvoton customers using or selling these products f or use in such applications do so at their own risk and agree to fully indemnify nuvoton for a ny damages resulting from such improper use or sales. www.datasheet.co.kr datasheet pdf - http://www..net/
ISD61S00 publication release date: march 10, 2011 - 27 - revision 2.7 table 7-1 status register description ............. ................................................... ...................... error! bookmark not defined. table 7-2 interrupt status register description... ................................................... ................ error! bookmark not defined. table 7-3 interrupt status register description... ................................................... ................ error! bookmark not defined. table 7-4 timer interrupt and operation status.... ................................................... ................ error! bookmark not defined. table 8-1 comp_cfg register compression type. ..... ................................................... ....... error! bookmark not defined. table 8-2 cfg0 sample rate control ................ ................................................... ................... error! bookmark not defined. table 8-3: pll frequency examples ................ ................................................... .................. error! bookmark not defined. table 8-4 microphone and auxiliary mode settings .. ................................................... ............. error! bookmark not defined. table 8-5 microphone gain settings ................ ................................................... ...................... error! bookmark not defined. table 8-6 microphone bias settings ................ ................................................... ...................... error! bookmark not defined. table 8-7 microphone resistor settings ............ ................................................... .................... error! bookmark not defined. table 8-8 ti gain settings ........................ ................................................... ............................ error! bookmark not defined. table 8-9 ti mux settings ......................... ................................................... ........................... error! bookmark not defined. table 8-11 dtmf frequency deviation register ...... ................................................... ............. error! bookmark not defined. table 8-12 tone generation mode setup ............. ................................................... ................ error! bookmark not defined. table 8-13 dtmf frequency mapping. ................ ................................................... ................. error! bookmark not defined. table 8-14 fsk encoder specification selection..... ................................................... .............. error! bookmark not defined. table 8-15 fsk detector modes. .................... ................................................... ...................... error! bookmark not defined. table 8-16 fsk_cmp_cnt definition. ................ ................................................... ................. error! bookmark not defined. table 8-17 cas detector frequency deviation control . ................................................. .......... error! bookmark not defined. table 8-18 cas/adt detection bits ................. ................................................... ..................... error! bookmark not defined. table 8-21 mixer gain registers. .................. ................................................... ........................ error! bookmark not defined. table 9-1 aec/lec control register map ............ ................................................... ................ error! bookmark not defined. table 9-2 sc gain table ........................... ................................................... ............................ error! bookmark not defined. table 10-1 spi commands ........................... ................................................... ........................ error! bookmark not defined. table 10-2 commands vs. status .................... ................................................... ..................... error! bookmark not defined. table 11-1 memory header........................... ................................................... ........................ error! bookmark not defined. table 11-2 the first byte of the memory header ... ................................................... .............. error! bookmark not defined. table 11-3 message header ......................... ................................................... ........................ error! bookmark not defined. www.datasheet.co.kr datasheet pdf - http://www..net/

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